Memories

class uvm.reg.uvm_mem.UVMMem(name, size, n_bits, access='RW', has_coverage=0)

Bases: UVMObject

Memory abstraction base class

A memory is a collection of contiguous locations. A memory may be accessible via more than one address map.

Unlike registers, memories are not mirrored because of the potentially large data space: tests that walk the entire memory space would negate any benefit from sparse memory modelling techniques. Rather than relying on a mirror, it is recommended that backdoor access be used instead.

m_max_size = 0

configure(parent, hdl_path='')

add_map(_map)

Xlock_modelX()

Xadd_vregX(vreg)

get_full_name()

Objects possessing hierarchy, such as <uvm_components>, override the default implementation. Other objects might be associated with component hierarchy but are not themselves components. For example, <uvm_sequence #(REQ,RSP)> classes are typically associated with a <uvm_sequencer #(REQ,RSP)>. In this case, it is useful to override get_full_name to return the sequencer’s full name concatenated with the sequence’s name. This provides the sequence a full context, which is useful when debugging.

Returns

The full hierarchical name of this object. The default implementation is the same as <get_name>, as uvm_objects do not inherently possess hierarchy.

Return type

str

get_parent()

get_block()

get_n_maps()

get_maps(maps)

get_local_map(_map, caller='')

get_default_map(caller='')

get_rights(_map=None)

get_access(_map=None)

get_size()

get_n_bytes()

get_n_bits()

classmethod get_max_size()

async write(status, offset, value, path=3, _map=None, parent=None, prior=-1, extension=None, fname='', lineno=0)

async read(status, offset, value, path=3, _map=None, parent=None, prior=-1, extension=None, fname='', lineno=0)

async burst_write(status, offset, value, path=3, _map=None, parent=None, prior=-1, extension=None, fname='', lineno=0)

async burst_read(status, offset, value, path=3, _map=None, parent=None, prior=-1, extension=None, fname='', lineno=0)

poke(status, offset, value, kind='', parent=None, extension=None, fname='', lineno=0)

peek(status, offset, value, kind='', parent=None, extension=None, fname='', lineno=0)

Xcheck_accessX(rw, map_info, caller)

async do_write(rw)

async do_read(rw)

set_backdoor(bkdr, fname='', lineno=0)

get_backdoor(inherited=1)

add_hdl_path_slice(name, offset, size, first=0, kind='RTL')

has_hdl_path(kind='')

get_full_hdl_path(paths, kind='', separator='.')

backdoor_read(rw)

backdoor_write(rw)

backdoor_read_func(rw)

async pre_write(rw)

async post_write(rw)

async pre_read(rw)

async post_read(rw)

build_coverage(models)

add_coverage(models)

has_coverage(models)

set_coverage(is_on)

get_coverage(is_on)

sample(offset, is_read, _map)

XsampleX(addr, is_read, _map)