Analysis Ports

Analysis Ports

This section defines the port, export, and imp classes used for transaction analysis.

class uvm.tlm1.uvm_analysis_port.UVMAnalysisPort(name, parent)

Bases: UVMPortBase

Broadcasts a value to all subscribers implementing a UVMAnalysisImp.

class mon(UVMComponent):

    def __init__(self, name="sb", parent=None):
        super.new(name, parent)
        self.ap = UVMAnalysisPort("ap", self)

    async def run_phase(self, phase):
        t = None
        ...
        self.ap.write(t)
        ...

get_type_name()

write(t)

Send specified value to all connected interface

Parameters

t (any) – Transaction to broadcast.

class uvm.tlm1.uvm_analysis_port.UVMAnalysisExport(name, parent=None)

Bases: UVMPortBase

Exports a lower-level UVMAnalysisImp to its parent. Export can be used to avoid long hierarchical paths like top.env.agent.monitor.

get_type_name()

write(t)

Analysis port differs from other ports in that it broadcasts to all connected interfaces. Ports only send to the interface at the index specified in a call to set_if (0 by default).

Parameters

t – Transaction to broadcast.