uvm_port_base

class uvm.base.uvm_port_base.UVMPortComponentBase(name, parent)

Bases: UVMComponent

This class defines an interface for obtaining a port’s connectivity lists after or during the end_of_elaboration phase. The sub-class, UVMPortComponent implements this interface.

The connectivity lists are returned in the form of handles to objects of this type. This allowing traversal of any port’s fan-out and fan-in network through recursive calls to <get_connected_to> and <get_provided_to>. Each port’s full name and type name can be retrieved using ~get_full_name~ and ~get_type_name~ methods inherited from <uvm_component>.

get_connected_to(port_list)

get_provided_to(port_list)

is_port()

Function: is_port

is_export()

Function: is_export

is_imp()

build_phase(phase)

Turn off auto config by not calling build_phase()

Parameters

phase –

do_task_phase(phase)

m_children: Dict[str, 'UVMComponent']

m_children_by_handle: Dict['UVMComponent', 'UVMComponent']

m_children_ordered: List['UVMComponent']

event_pool: UVMEventPool

class uvm.base.uvm_port_base.UVMPortComponent(name, parent, port)

Bases: UVMPortComponentBase

See description of UVMPortComponentBase for information about this class

get_type_name()

This function returns the type name of the object, which is typically the type identifier enclosed in quotes. It is used for various debugging functions in the library, and it is used by the factory for creating objects.

This function must be defined in every derived class.

A typical implementation is as follows:

class mytype (UVMObject):
  ...
  type_name = "mytype"

  def get_type_name(self):
    return my_type.type_name

We define the type_name static variable to enable access to the type name without need of an object of the class, i.e., to enable access via the scope operator, ~mytype::type_name~.

Returns

Type name of the object.

Return type

str

resolve_bindings()

Processes all port, export, and imp connections. Checks whether each port’s min and max connection requirements are met.

It is called just before the end_of_elaboration phase.

Users should not call directly.

get_port()

Function: get_port

Retrieve the actual port object that this proxy refers to. Returns:

get_connected_to(port_list)

get_provided_to(port_list)

is_port()

Function: is_port

is_export()

Function: is_export

is_imp()

m_children: Dict[str, 'UVMComponent']

m_children_by_handle: Dict['UVMComponent', 'UVMComponent']

m_children_ordered: List['UVMComponent']

event_pool: UVMEventPool

class uvm.base.uvm_port_base.UVMPortBase(name, parent, port_type, min_size=0, max_size=1)

Bases: object

Transaction-level communication between components is handled via its ports, exports, and imps, all of which derive from this class.

The UVM provides a complete set of ports, exports, and imps for the OSCI- standard TLM interfaces. They can be found in the ../src/tlm/ directory.

Just before UVMComponent.end_of_elaboration_phase, an internal UVMComponent.resolve_bindings process occurs, after which each port and export holds a list of all imps connected to it via hierarchical connections to other ports and exports. In effect, we are collapsing the port’s fanout, which can span several levels up and down the component hierarchy, into a single array held local to the port. Once the list is determined, the port’s min and max connection settings can be checked and enforced.

uvm_port_base possesses the properties of components in that they have a hierarchical instance path and parent. Because SystemVerilog does not support multiple inheritance, uvm_port_base cannot extend both the interface it implements and <uvm_component>. Thus, uvm_port_base contains a local instance of uvm_component, to which it delegates such commands as get_name, get_full_name, and get_parent.

get_name()

Returns the leaf name of this port.

get_full_name()

Returns the full hierarchical name of this port.

get_parent()

Returns the handle to this port’s parent, or ~null~ if it has no parent.

get_comp()

get_type_name()

max_size()

Function: max_size

Returns the maximum number of implementation ports that must be connected to this port by the end_of_elaboration phase. Returns:

min_size()

Function: min_size

Returns the minimum number of implementation ports that must be connected to this port by the end_of_elaboration phase. Returns:

is_unbounded()

is_port()

is_export()

is_imp()

size()

set_if(index=0)

m_get_if_mask()

set_default_index(index)

connect(provider)

Function: connect

Connects this port to the given provider port. The ports must be compatible in the following ways

• Their type parameters must match

• The provider’s interface type (blocking, non-blocking, analysis, etc.)

  must be compatible. Each port has an interface mask that encodes the interface(s) it supports. If the bitwise AND of these masks is equal to the this port’s mask, the requirement is met and the ports are compatible. For example, a uvm_blocking_put_port #(T) is compatible with a uvm_put_export #(T) and uvm_blocking_put_imp #(T) because the export and imp provide the interface required by the uvm_blocking_put_port.

• Ports of type UVM_EXPORT can only connect to other exports or imps.

• Ports of type UVM_IMPLEMENTATION cannot be connected, as they are

  bound to the component that implements the interface at time of construction.

In addition to type-compatibility checks, the relationship between this port and the provider port will also be checked if the port’s check_connection_relationships configuration has been set. (See new for more information.)

Relationships, when enabled, are checked are as follows:

• If this port is a UVM_PORT type, the provider can be a parent port,

  or a sibling export or implementation port.

• If this port is a UVM_EXPORT type, the provider can be a child

  export or implementation port.

If any relationship check is violated, a warning is issued.

Note- the UVMComponent.connect_phase method is related to but not the same as this method. The component’s connect method is a phase callback where port’s connect method calls are made. :param provider:

indent = ''

save = ''

debug_connected_to(level=0, max_level=-1)

debug_provided_to(level=0, max_level=-1)

get_connected_to(port_list)

get_provided_to(port_list)

m_check_relationship(provider)

m_add_list(provider)

Internal method. :param provider:

resolve_bindings()

get_if(index=0)