uvm-python Class Reference

Base

• Overview
• uvm_void
• uvm_object
• uvm_transaction
• uvm_root
• uvm_port_base

Reporting

• Overview
• uvm_report_message
• uvm_report_object
• uvm_report_handler
• uvm_report_server
• uvm_report_catcher

Recording

• Overview
• uvm_tr_database
• uvm_tr_stream

Factory

• Overview
• uvm_*_registry
• uvm_factory

Phasing

• Overview
• uvm_phase
• uvm_domain
• uvm_bottomup_phase
• uvm_task_phase
• uvm_topdown_phase
• UVM Common Phases
• UVM Run-Time Phases
• User-Defined Phases

Configuration and Resources

• Overview
• uvm_resource
• uvm_resource_db
• uvm_config_db

Synchronization

• Overview
• uvm_event
• uvm_event_callback
• uvm_barrier
• uvm_objection
• uvm_heartbeat
• uvm_callback

Containers

• Overview
• uvm_pool
• uvm_queue

TLM

• Overview

TLM1

• Overview
• Interfaces
• Ports
• Exports
• Imps
• FIFO
• FIFO Base
• Request-Response Channel
• Sequence Item Pull Ports
• Sequencer Base

TLM2

• Overview
• Interface Masks
• TLM2 Types
• TLM Generic Payload & Extensions
• TLM Socket Base Classes
• TLM Sockets
• TLM2 Export Classes
• TLM2 imps (interface implementations)
• TLM2 ports
• uvm_tlm_time
• Analysis Ports

Components

• Overview
• uvm_component
• uvm_test
• uvm_env
• uvm_agent
• uvm_monitor
• uvm_scoreboard
• uvm_driver
• uvm_push_driver
• uvm_random_stimulus
• uvm_subscriber

Comparators

• Overview
• uvm_in_order_comparator
• uvm_algorithmic_comparator
• uvm_pair
• uvm_policies

Sequencers

• Overview
• uvm_sequencer_base
• uvm_sequencer_param_base
• uvm_sequencer
• uvm_push_sequencer

Sequences

• Overview
• uvm_sequence_item
• uvm_sequence_base
• uvm_sequence
• uvm_sequence_library

Macros

• Overview
• Report Macros
• Global Macros
• Component and Object
• Sequence and Do Action
• Callbacks
• TLM
• Registers
• Version Macros

Policies

• Overview
• uvm_printer
• uvm_comparer
• uvm_recorder
• uvm_packer
• Links

Data Access

• Overview
• Set/Get Base
• Simple Lock
• Get-To-Lock
• Set-Before-Get

Register Layer

• Overview
• Globals

Register Model

• Blocks
• Address Maps
• Register Files
• Registers
• Fields
• Memories
• Indirect Registers
• FIFO Registers
• Virtual Registers
• Virtual Fields
• Callbacks
• Memory Allocation Mgr

DUT Integration

• Generic Register Operation Descriptors
• Register Model Adaptor
• Explicit Register Predictor
• Register Sequences
• Backdoors
• HDL access

Test Sequences

• Run All Built-In
• Reset
• Register Bit Bash
• Register Access
• Shared Access
• Memory Access
• Memory Walk
• HDL Paths Checking

Command Line Processor

• Overview
• uvm_cmdline_processor

Globals

• Overview
• Types, Enums, Policies
• Globals
• UVM Core Service
• UVM Traversal