Blocks

class uvm.reg.uvm_reg_block.UVMRegBlock(name='', has_coverage=0)

Bases: uvm.base.uvm_object.UVMObject

Block abstraction base class

A block represents a design hierarchy. It can contain registers, register files, memories and sub-blocks.

A block has one or more address maps, each corresponding to a physical interface on the block.

m_roots: Dict[uvm.reg.uvm_reg_block.UVMRegBlock, int] = {}

id = 0

configure(parent=None, hdl_path='')

create_map(name: str, base_addr: int, n_bytes: int, endian: int, byte_addressing=True) → Optional[uvm.reg.uvm_reg_map.UVMRegMap]

check_data_width(width: int) → int

set_default_map(_map: uvm.reg.uvm_reg_map.UVMRegMap)

get_default_map() → uvm.reg.uvm_reg_map.UVMRegMap

set_parent(parent: uvm.reg.uvm_reg_block.UVMRegBlock)

add_block(blk: uvm.reg.uvm_reg_block.UVMRegBlock)

add_map(_map: uvm.reg.uvm_reg_map.UVMRegMap)

add_reg(rg: uvm.reg.uvm_reg.UVMReg)

add_vreg(vreg)

add_mem(mem: uvm.reg.uvm_mem.UVMMem)

lock_model()

is_locked()

get_full_name() → str

Objects possessing hierarchy, such as <uvm_components>, override the default implementation. Other objects might be associated with component hierarchy but are not themselves components. For example, <uvm_sequence #(REQ,RSP)> classes are typically associated with a <uvm_sequencer #(REQ,RSP)>. In this case, it is useful to override get_full_name to return the sequencer’s full name concatenated with the sequence’s name. This provides the sequence a full context, which is useful when debugging.

Returns

The full hierarchical name of this object. The default implementation is the same as <get_name>, as uvm_objects do not inherently possess hierarchy.

Return type

str

get_parent() → Optional[uvm.reg.uvm_reg_block.UVMRegBlock]

get_root_blocks(blks)

get_blocks(blks, hier=1)

get_maps(maps)

get_registers(regs, hier=1)

get_memories(mems, hier=1)

get_map_by_name(name) → Optional[uvm.reg.uvm_reg_map.UVMRegMap]

get_reg_by_name(name) → Optional[uvm.reg.uvm_reg.UVMReg]

build_coverage(models)

add_coverage(models)

has_coverage(models)

set_coverage(is_on)

get_coverage(is_on=- 1)

sample(offset, is_read, _map)

sample_values()

XsampleX(addr, is_read, _map)

get_default_path()

reset(kind='HARD')

needs_update()

async update(status, path=3, parent=None, prior=- 1, extension=None, fname='', lineno=0)

async mirror(status, check=0, path=3, parent=None, prior=- 1, extension=None, fname='', lineno=0)

async write_reg_by_name(status, name, data, path=3, map=None, parent=None, prior=- 1, extension=None, fname='', lineno=0)

get_backdoor(inherited=True)

add_hdl_path(path, kind='RTL')

has_hdl_path(kind='')

get_full_hdl_path(paths, kind='', separator='.')

set_default_hdl_path(kind: str)

get_default_hdl_path() → str

set_hdl_path_root(path, kind='RTL')

is_hdl_path_root(kind='')

Xinit_address_mapsX()