FIFO Base

class uvm.tlm1.uvm_tlm_fifo_base.UVMTLMEvent[source]

Bases: object

class uvm.tlm1.uvm_tlm_fifo_base.UVMTLMFIFOBase(name, parent=None)[source]

Bases: UVMComponent

This class is the base for UVMTLMFIFO. It defines the TLM exports through which all transaction-based FIFO operations occur. It also defines default implementations for each interface method provided by these exports.

The interface methods provided by the put_export and the get_peek_export are defined and described by UVMTLMIfBase. See the TLM Overview section for a general discussion of TLM interface definition and usage.

Variables

put_export (UVMPutImp) –

The put_export provides both the blocking and non-blocking put interface methods to any attached port:

Example:

task put (input T t)
function bit can_put ()
function bit try_put (input T t)

Any put port variant can connect and send transactions to the FIFO via this export, provided the transaction types match. See UVMTLMIfBase for more information on each of the above interface methods.

Variables

get_peek_export (UVMGetPeekImp) –

The get_peek_export provides all the blocking and non-blocking get and peek interface methods:

task get (output T t)
function bit can_get ()
function bit try_get (output T t)
task peek (output T t)
function bit can_peek ()
function bit try_peek (output T t)

Any get or peek port variant can connect to and retrieve transactions from the FIFO via this export, provided the transaction types match. See <uvm_tlm_if_base #(T1,T2)> for more information on each of the above interface methods.

Variables

put_ap (UVMAnalysisPort) –

Transactions passed via put or try_put (via any port connected to the <put_export>) are sent out this port via its write method.

def write (T t)

All connected analysis exports and imps will receive put transactions. See <uvm_tlm_if_base #(T1,T2)> for more information on the write interface method.

Variables

get_ap (UVMAnalysisPort) –

Transactions passed via get, try_get, peek, or try_peek (via any port connected to the <get_peek_export>) are sent out this port via its write method.

def write (T t)

All connected analysis exports and imps will receive get transactions. See <uvm_tlm_if_base #(T1,T2)> for more information on the write method.

The following are aliases to the above put_export.

Variables
  • blocking_put_export (UVMPutImp) –

  • nonblocking_put_export (UVMPutImp) –

The following are all aliased to the above get_peek_export, which provides the superset of these interfaces.

Variables
  • blocking_get_export (UVMGetPeekImp) –

  • nonblocking_get_export (UVMGetPeekImp) –

  • get_export (UVMGetPeekImp) –

  • blocking_peek_export (UVMGetPeekImp) –

  • nonblocking_peek_export (UVMGetPeekImp) –

  • peek_export (UVMGetPeekImp) –

  • blocking_get_peek_export (UVMGetPeekImp) –

  • nonblocking_get_peek_export (UVMGetPeekImp) –

build_phase(phase)[source]
Parameters

phase (UVMPhase) –

flush()[source]
size()[source]
async put(t)[source]
async get(t)[source]
async peek(t)[source]
try_put(t)[source]
try_get(t)[source]
try_peek(t)[source]
can_put()[source]
can_get()[source]
can_peek()[source]
ok_to_put()[source]
ok_to_get()[source]
ok_to_peek()[source]
is_empty()[source]
is_full()[source]
used()[source]
m_children: Dict[str, 'UVMComponent']
m_children_by_handle: Dict['UVMComponent', 'UVMComponent']
m_children_ordered: List['UVMComponent']
event_pool: UVMEventPool